package sifive.blocks.devices.spi
import Chisel._
-import diplomacy.LazyModule
-import uncore.tilelink2._
-import rocketchip.{TopNetwork,TopNetworkModule}
-
-trait PeripherySPI {
- this: TopNetwork { val spiConfigs: Seq[SPIConfig] } =>
- val spiDevices = (spiConfigs.zipWithIndex) map {case (c, i) =>
- val spi = LazyModule(new TLSPI(c) { override lazy val valName = Some(s"spi$i") } )
- spi.rnode := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
- intBus.intnode := spi.intnode
+import freechips.rocketchip.config.Field
+import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
+import freechips.rocketchip.diplomacy.{LazyModule,LazyMultiIOModuleImp,BufferParams}
+import freechips.rocketchip.tilelink.{TLFragmenter,TLBuffer}
+import freechips.rocketchip.util.HeterogeneousBag
+
+case object PeripherySPIKey extends Field[Seq[SPIParams]]
+
+trait HasPeripherySPI extends HasPeripheryBus with HasInterruptBus {
+ val spiParams = p(PeripherySPIKey)
+ val spis = spiParams map { params =>
+ val spi = LazyModule(new TLSPI(pbus.beatBytes, params))
+ spi.rnode := pbus.toVariableWidthSlaves
+ ibus.fromSync := spi.intnode
spi
}
}
-trait PeripherySPIBundle {
- this: { val spiConfigs: Seq[SPIConfig] } =>
- val spi_bc = spiConfigs.map(_.bc).reduce(_.union(_))
- val spis = Vec(spiConfigs.size, new SPIPortIO(spi_bc.toSPIConfig))
+trait HasPeripherySPIBundle {
+ val spi: HeterogeneousBag[SPIPortIO]
+
}
-trait PeripherySPIModule {
- this: TopNetworkModule {
- val spiConfigs: Seq[SPIConfig]
- val outer: PeripherySPI
- val io: PeripherySPIBundle
- } =>
- (io.spis zip outer.spiDevices).foreach { case (io, device) =>
+trait HasPeripherySPIModuleImp extends LazyMultiIOModuleImp with HasPeripherySPIBundle {
+ val outer: HasPeripherySPI
+ val spi = IO(HeterogeneousBag(outer.spiParams.map(new SPIPortIO(_))))
+
+ (spi zip outer.spis).foreach { case (io, device) =>
io <> device.module.io.port
}
}
+case object PeripherySPIFlashKey extends Field[Seq[SPIFlashParams]]
-trait PeripherySPIFlash {
- this: TopNetwork { val spiFlashConfig: SPIFlashConfig } =>
- val qspi = LazyModule(new TLSPIFlash(spiFlashConfig))
- qspi.rnode := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
- qspi.fnode := TLFragmenter(1, cacheBlockBytes)(TLWidthWidget(peripheryBusConfig.beatBytes)(peripheryBus.node))
- intBus.intnode := qspi.intnode
+trait HasPeripherySPIFlash extends HasPeripheryBus with HasInterruptBus {
+ val spiFlashParams = p(PeripherySPIFlashKey)
+ val qspis = spiFlashParams map { params =>
+ val qspi = LazyModule(new TLSPIFlash(pbus.beatBytes, params))
+ qspi.rnode := pbus.toVariableWidthSlaves
+ qspi.fnode :=
+ TLFragmenter(1, pbus.blockBytes)(
+ TLBuffer(BufferParams(params.fBufferDepth), BufferParams.none)(
+ pbus.toFixedWidthSlaves))
+ ibus.fromSync := qspi.intnode
+ qspi
+ }
}
-trait PeripherySPIFlashBundle {
- this: { val spiFlashConfig: SPIFlashConfig } =>
- val qspi = new SPIPortIO(spiFlashConfig)
+trait HasPeripherySPIFlashBundle {
+ val qspi: HeterogeneousBag[SPIPortIO]
+
}
-trait PeripherySPIFlashModule {
- this: TopNetworkModule {
- val spiConfigs: Seq[SPIConfig]
- val outer: PeripherySPIFlash
- val io: PeripherySPIFlashBundle
- } =>
- io.qspi <> outer.qspi.module.io.port
+trait HasPeripherySPIFlashModuleImp extends LazyMultiIOModuleImp with HasPeripherySPIFlashBundle {
+ val outer: HasPeripherySPIFlash
+ val qspi = IO(HeterogeneousBag(outer.spiFlashParams.map(new SPIPortIO(_))))
+
+ (qspi zip outer.qspis) foreach { case (io, device) =>
+ io <> device.module.io.port
+ }
}