package sifive.blocks.devices.spi
import Chisel._
-import sifive.blocks.util.ShiftRegisterInit
+import freechipchips.rocketchip.util.ShiftRegInit
-class SPIMicroOp(c: SPIConfigBase) extends SPIBundle(c) {
+class SPIMicroOp(c: SPIParamsBase) extends SPIBundle(c) {
val fn = Bits(width = 1)
val stb = Bool()
val cnt = UInt(width = c.countBits)
def Delay = UInt(1, 1)
}
-class SPIPhyControl(c: SPIConfigBase) extends SPIBundle(c) {
+class SPIPhyControl(c: SPIParamsBase) extends SPIBundle(c) {
val sck = new SPIClocking(c)
val fmt = new SPIFormat(c)
}
-class SPIPhysical(c: SPIConfigBase) extends Module {
+class SPIPhysical(c: SPIParamsBase) extends Module {
val io = new SPIBundle(c) {
val port = new SPIPortIO(c)
val ctrl = new SPIPhyControl(c).asInput
val last = Wire(init = Bool(false))
// Delayed versions
val setup_d = Reg(next = setup)
- val sample_d = ShiftRegisterInit(sample, c.sampleDelay, Bool(false))
- val last_d = ShiftRegisterInit(last, c.sampleDelay, Bool(false))
+ val sample_d = ShiftRegInit(sample, c.sampleDelay, init = Bool(false))
+ val last_d = ShiftRegInit(last, c.sampleDelay, init = Bool(false))
val scnt = Reg(init = UInt(0, c.countBits))
val tcnt = Reg(io.ctrl.sck.div)
}
val tx = (ctrl.fmt.iodir === SPIDirection.Tx)
- val txen_in = (proto.head +: proto.tail.map(_ && tx)).scanRight(Bool(false))(_ || _)
+ val txen_in = (proto.head +: proto.tail.map(_ && tx)).scanRight(Bool(false))(_ || _).init
val txen = txen_in :+ txen_in.last
io.port.sck := sck