package sifive.blocks.devices.uart
import Chisel._
-import config._
-import regmapper._
-import uncore.tilelink2._
-import util._
+import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.coreplex.RTCPeriod
+import freechips.rocketchip.diplomacy.DTSTimebase
+import freechips.rocketchip.regmapper._
+import freechips.rocketchip.tilelink._
+import freechips.rocketchip.util._
import sifive.blocks.util.{NonBlockingEnqueue, NonBlockingDequeue}
val rxm = Module(new UARTRx(params))
val rxq = Module(new Queue(rxm.io.out.bits, uartNRxEntries))
- val divinit = 542 // (62.5MHz / 115200)
+ val divinit = p(DTSTimebase) * BigInt(p(RTCPeriod).getOrElse(1)) / 115200
val div = Reg(init = UInt(divinit, uartDivisorBits))
private val stopCountBits = log2Up(uartStopBits)