package sifive.blocks.devices.uart
import Chisel._
-import config._
-import diplomacy._
-import uncore.tilelink2._
-import rocketchip._
-
-import sifive.blocks.devices.gpio.{GPIOPin, GPIOOutputPinCtrl, GPIOInputPinCtrl}
+import chisel3.experimental.{withClockAndReset}
+import freechips.rocketchip.config.Field
+import freechips.rocketchip.coreplex.{HasPeripheryBus, PeripheryBusParams, HasInterruptBus}
+import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
+import sifive.blocks.devices.pinctrl.{Pin}
import sifive.blocks.util.ShiftRegisterInit
-trait PeripheryUART {
- this: TopNetwork {
- val uartConfigs: Seq[UARTConfig]
- } =>
- val uart = uartConfigs.zipWithIndex.map { case (c, i) =>
- val uart = LazyModule(new UART(c))
- uart.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
- intBus.intnode := uart.intnode
+case object PeripheryUARTKey extends Field[Seq[UARTParams]]
+
+trait HasPeripheryUART extends HasPeripheryBus with HasInterruptBus {
+ private val divinit = (p(PeripheryBusParams).frequency / 115200).toInt
+ val uartParams = p(PeripheryUARTKey).map(_.copy(divisorInit = divinit))
+ val uarts = uartParams map { params =>
+ val uart = LazyModule(new TLUART(pbus.beatBytes, params))
+ uart.node := pbus.toVariableWidthSlaves
+ ibus.fromSync := uart.intnode
uart
}
}
-trait PeripheryUARTBundle {
- this: { val uartConfigs: Seq[UARTConfig] } =>
- val uarts = Vec(uartConfigs.size, new UARTPortIO)
+trait HasPeripheryUARTBundle {
+ val uart: Vec[UARTPortIO]
+
+ def tieoffUARTs(dummy: Int = 1) {
+ uart.foreach { _.rxd := UInt(1) }
+ }
+
}
-trait PeripheryUARTModule {
- this: TopNetworkModule {
- val outer: PeripheryUART
- val io: PeripheryUARTBundle
- } =>
- (io.uarts zip outer.uart).foreach { case (io, device) =>
+trait HasPeripheryUARTModuleImp extends LazyMultiIOModuleImp with HasPeripheryUARTBundle {
+ val outer: HasPeripheryUART
+ val uart = IO(Vec(outer.uartParams.size, new UARTPortIO))
+
+ (uart zip outer.uarts).foreach { case (io, device) =>
io <> device.module.io.port
}
}
-class UARTPinsIO extends Bundle {
- val rxd = new GPIOPin
- val txd = new GPIOPin
-}
+class UARTPins[T <: Pin] (pingen: () => T) extends Bundle {
+ val rxd = pingen()
+ val txd = pingen()
-class UARTGPIOPort(syncStages: Int = 0) extends Module {
- val io = new Bundle{
- val uart = new UARTPortIO().flip()
- val pins = new UARTPinsIO
- }
+ override def cloneType: this.type =
+ this.getClass.getConstructors.head.newInstance(pingen).asInstanceOf[this.type]
- GPIOOutputPinCtrl(io.pins.txd, io.uart.txd)
- val rxd = GPIOInputPinCtrl(io.pins.rxd)
- io.uart.rxd := ShiftRegisterInit(rxd, syncStages, Bool(true))
+ def fromPort(uart: UARTPortIO, clock: Clock, reset: Bool, syncStages: Int = 0) {
+ withClockAndReset(clock, reset) {
+ txd.outputPin(uart.txd)
+ val rxd_t = rxd.inputPin()
+ uart.rxd := ShiftRegisterInit(rxd_t, syncStages, Bool(true))
+ }
+ }
}
+