package sifive.blocks.devices.xilinxvc707mig
import Chisel._
+import chisel3.experimental.{Analog,attach}
import config._
import diplomacy._
import uncore.tilelink2._
import uncore.axi4._
import rocketchip._
-import sifive.blocks.ip.xilinx.vc707mig.{VC707MIGUnidirectionalIOClocksReset, VC707MIGUnidirectionalIODDR, vc707mig}
+import sifive.blocks.ip.xilinx.vc707mig.{VC707MIGIOClocksReset, VC707MIGIODDR, vc707mig}
trait HasXilinxVC707MIGParameters {
}
-class XilinxVC707MIGPads extends Bundle with VC707MIGUnidirectionalIODDR {
- val _inout_ddr3_dq = Bits(OUTPUT,64)
- val _inout_ddr3_dqs_n = Bits(OUTPUT,8)
- val _inout_ddr3_dqs_p = Bits(OUTPUT,8)
-}
+class XilinxVC707MIGPads extends Bundle with VC707MIGIODDR
-class XilinxVC707MIGIO extends Bundle with VC707MIGUnidirectionalIODDR
- with VC707MIGUnidirectionalIOClocksReset {
- val _inout_ddr3_dq = Bits(OUTPUT,64)
- val _inout_ddr3_dqs_n = Bits(OUTPUT,8)
- val _inout_ddr3_dqs_p = Bits(OUTPUT,8)
-}
+class XilinxVC707MIGIO extends Bundle with VC707MIGIODDR
+ with VC707MIGIOClocksReset
class XilinxVC707MIG(implicit p: Parameters) extends LazyModule with HasXilinxVC707MIGParameters {
val device = new MemoryDevice
regionType = RegionType.UNCACHED,
executable = true,
supportsWrite = TransferSizes(1, 256*8),
- supportsRead = TransferSizes(1, 256*8),
- interleavedId = Some(0))),
+ supportsRead = TransferSizes(1, 256*8))),
beatBytes = 8)))
- val xing = LazyModule(new TLAsyncCrossing)
- val toaxi4 = LazyModule(new TLToAXI4(idBits = 4))
+ val xing = LazyModule(new TLAsyncCrossing)
+ val toaxi4 = LazyModule(new TLToAXI4(beatBytes = 8))
+ val indexer = LazyModule(new AXI4IdIndexer(idBits = 4))
+ val deint = LazyModule(new AXI4Deinterleaver(p(coreplex.CacheBlockBytes)))
+ val yank = LazyModule(new AXI4UserYanker)
+ val buffer = LazyModule(new AXI4Buffer)
xing.node := node
val monitor = (toaxi4.node := xing.node)
- axi4 := toaxi4.node
+ axi4 := buffer.node
+ buffer.node := yank.node
+ yank.node := deint.node
+ deint.node := indexer.node
+ indexer.node := toaxi4.node
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
//pins to top level
//inouts
- io.port._inout_ddr3_dq := blackbox.io.ddr3_dq
- io.port._inout_ddr3_dqs_n := blackbox.io.ddr3_dqs_n
- io.port._inout_ddr3_dqs_p := blackbox.io.ddr3_dqs_p
+ attach(io.port.ddr3_dq,blackbox.io.ddr3_dq)
+ attach(io.port.ddr3_dqs_n,blackbox.io.ddr3_dqs_n)
+ attach(io.port.ddr3_dqs_p,blackbox.io.ddr3_dqs_p)
//outputs
io.port.ddr3_addr := blackbox.io.ddr3_addr
io.port.ddr3_odt := blackbox.io.ddr3_odt
//inputs
- //differential system clock
- blackbox.io.sys_clk_n := io.port.sys_clk_n
- blackbox.io.sys_clk_p := io.port.sys_clk_p
+ //NO_BUFFER clock
+ blackbox.io.sys_clk_i := io.port.sys_clk_i
//user interface signals
val axi_async = axi4.bundleIn(0)
xing.module.io.in_reset := reset
xing.module.io.out_clock := blackbox.io.ui_clk
xing.module.io.out_reset := blackbox.io.ui_clk_sync_rst
- toaxi4.module.clock := blackbox.io.ui_clk
- toaxi4.module.reset := blackbox.io.ui_clk_sync_rst
- monitor.foreach { lm =>
+ (Seq(toaxi4, indexer, deint, yank, buffer) ++ monitor) foreach { lm =>
lm.module.clock := blackbox.io.ui_clk
lm.module.reset := blackbox.io.ui_clk_sync_rst
}