package sifive.blocks.devices.xilinxvc707pciex1
import Chisel._
-import diplomacy.LazyModule
-import rocketchip.{
- HasTopLevelNetworks,
- HasTopLevelNetworksModule,
- HasTopLevelNetworksBundle
-}
-import uncore.tilelink2.TLWidthWidget
-
-trait HasPeripheryXilinxVC707PCIeX1 extends HasTopLevelNetworks {
+import freechips.rocketchip.coreplex.{HasInterruptBus, HasSystemBus}
+import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
+trait HasSystemXilinxVC707PCIeX1 extends HasSystemBus with HasInterruptBus {
val xilinxvc707pcie = LazyModule(new XilinxVC707PCIeX1)
- l2FrontendBus.node := xilinxvc707pcie.master
- xilinxvc707pcie.slave := TLWidthWidget(socBusConfig.beatBytes)(socBus.node)
- xilinxvc707pcie.control := TLWidthWidget(socBusConfig.beatBytes)(socBus.node)
- intBus.intnode := xilinxvc707pcie.intnode
+
+ sbus.fromAsyncFIFOMaster() := xilinxvc707pcie.master
+ xilinxvc707pcie.slave := sbus.toAsyncFixedWidthSlaves()
+ xilinxvc707pcie.control := sbus.toAsyncFixedWidthSlaves()
+ ibus.fromAsync := xilinxvc707pcie.intnode
}
-trait HasPeripheryXilinxVC707PCIeX1Bundle extends HasTopLevelNetworksBundle {
- val xilinxvc707pcie = new XilinxVC707PCIeX1IO
+trait HasSystemXilinxVC707PCIeX1Bundle {
+ val xilinxvc707pcie: XilinxVC707PCIeX1IO
+ def connectXilinxVC707PCIeX1ToPads(pads: XilinxVC707PCIeX1Pads) {
+ pads <> xilinxvc707pcie
+ }
}
-trait HasPeripheryXilinxVC707PCIeX1Module extends HasTopLevelNetworksModule {
- val outer: HasPeripheryXilinxVC707PCIeX1
- val io: HasPeripheryXilinxVC707PCIeX1Bundle
+trait HasSystemXilinxVC707PCIeX1ModuleImp extends LazyMultiIOModuleImp
+ with HasSystemXilinxVC707PCIeX1Bundle {
+ val outer: HasSystemXilinxVC707PCIeX1
+ val xilinxvc707pcie = IO(new XilinxVC707PCIeX1IO)
+
+ xilinxvc707pcie <> outer.xilinxvc707pcie.module.io.port
- io.xilinxvc707pcie <> outer.xilinxvc707pcie.module.io.port
+ outer.xilinxvc707pcie.module.clock := outer.xilinxvc707pcie.module.io.port.axi_aclk_out
+ outer.xilinxvc707pcie.module.reset := ~xilinxvc707pcie.axi_aresetn
}