i965/blorp: Make post draw flush more explicit
[mesa.git] / src / mesa / drivers / dri / i965 / genX_blorp_exec.c
index 03c13b7bba145202f0c9f84becda6a724331d199..647a362afe04325863d99066d60282f07b8ae95d 100644 (file)
 
 #include "intel_batchbuffer.h"
 #include "intel_mipmap_tree.h"
+#include "intel_fbo.h"
 
 #include "brw_context.h"
 #include "brw_state.h"
 
-#include "genX_blorp_exec.h"
+#include "blorp/blorp_genX_exec.h"
 
 #include "brw_blorp.h"
 
@@ -55,12 +56,12 @@ blorp_emit_reloc(struct blorp_batch *batch,
 
    uint32_t offset = (char *)location - (char *)brw->batch.map;
    if (brw->gen >= 8) {
-      return intel_batchbuffer_reloc64(brw, address.buffer, offset,
+      return intel_batchbuffer_reloc64(&brw->batch, address.buffer, offset,
                                        address.read_domains,
                                        address.write_domain,
                                        address.offset + delta);
    } else {
-      return intel_batchbuffer_reloc(brw, address.buffer, offset,
+      return intel_batchbuffer_reloc(&brw->batch, address.buffer, offset,
                                      address.read_domains,
                                      address.write_domain,
                                      address.offset + delta);
@@ -104,20 +105,21 @@ blorp_alloc_dynamic_state(struct blorp_batch *batch,
 static void
 blorp_alloc_binding_table(struct blorp_batch *batch, unsigned num_entries,
                           unsigned state_size, unsigned state_alignment,
-                          uint32_t *bt_offset, uint32_t **bt_map,
+                          uint32_t *bt_offset, uint32_t *surface_offsets,
                           void **surface_maps)
 {
    assert(batch->blorp->driver_ctx == batch->driver_batch);
    struct brw_context *brw = batch->driver_batch;
 
-   *bt_map = brw_state_batch(brw, AUB_TRACE_BINDING_TABLE,
-                             num_entries * sizeof(uint32_t), 32,
-                             bt_offset);
+   uint32_t *bt_map = brw_state_batch(brw, AUB_TRACE_BINDING_TABLE,
+                                      num_entries * sizeof(uint32_t), 32,
+                                      bt_offset);
 
    for (unsigned i = 0; i < num_entries; i++) {
       surface_maps[i] = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
                                         state_size, state_alignment,
-                                        &(*bt_map)[i]);
+                                        &(surface_offsets)[i]);
+      bt_map[i] = surface_offsets[i];
    }
 }
 
@@ -161,22 +163,9 @@ blorp_emit_urb_config(struct blorp_batch *batch, unsigned vs_entry_size)
 #endif
 }
 
-static void
-blorp_emit_3dstate_multisample(struct blorp_batch *batch, unsigned samples)
-{
-   assert(batch->blorp->driver_ctx == batch->driver_batch);
-   struct brw_context *brw = batch->driver_batch;
-
-#if GEN_GEN >= 8
-   gen8_emit_3dstate_multisample(brw, samples);
-#else
-   gen6_emit_3dstate_multisample(brw, samples);
-#endif
-}
-
 void
 genX(blorp_exec)(struct blorp_batch *batch,
-                 const struct brw_blorp_params *params)
+                 const struct blorp_params *params)
 {
    assert(batch->blorp->driver_ctx == batch->driver_batch);
    struct brw_context *brw = batch->driver_batch;
@@ -191,7 +180,9 @@ genX(blorp_exec)(struct blorp_batch *batch,
     * data with different formats, which blorp does for stencil and depth
     * data.
     */
-   brw_emit_mi_flush(brw);
+   if (params->src.enabled)
+      brw_render_cache_set_check_flush(brw, params->src.addr.buffer);
+   brw_render_cache_set_check_flush(brw, params->dst.addr.buffer);
 
    brw_select_pipeline(brw, BRW_RENDER_PIPELINE);
 
@@ -218,6 +209,15 @@ retry:
 
    brw_emit_depth_stall_flushes(brw);
 
+#if GEN_GEN == 8
+   gen8_write_pma_stall_bits(brw, 0);
+#endif
+
+   blorp_emit(batch, GENX(3DSTATE_DRAWING_RECTANGLE), rect) {
+      rect.ClippedDrawingRectangleXMax = MAX2(params->x1, params->x0) - 1;
+      rect.ClippedDrawingRectangleYMax = MAX2(params->y1, params->y0) - 1;
+   }
+
    blorp_exec(batch, params);
 
    /* Make sure we didn't wrap the batch unintentionally, and make sure we
@@ -259,8 +259,6 @@ retry:
    brw->no_depth_or_stencil = false;
    brw->ib.type = -1;
 
-   /* Flush the sampler cache so any texturing from the destination is
-    * coherent.
-    */
-   brw_emit_mi_flush(brw);
+   if (params->dst.enabled)
+      brw_render_cache_set_add_bo(brw, params->dst.addr.buffer);
 }