i965/blorp: Make post draw flush more explicit
[mesa.git] / src / mesa / drivers / dri / i965 / genX_blorp_exec.c
index 8cd5a62bf092c190291e95b8846e5fed99bdd264..647a362afe04325863d99066d60282f07b8ae95d 100644 (file)
@@ -25,6 +25,7 @@
 
 #include "intel_batchbuffer.h"
 #include "intel_mipmap_tree.h"
+#include "intel_fbo.h"
 
 #include "brw_context.h"
 #include "brw_state.h"
@@ -55,12 +56,12 @@ blorp_emit_reloc(struct blorp_batch *batch,
 
    uint32_t offset = (char *)location - (char *)brw->batch.map;
    if (brw->gen >= 8) {
-      return intel_batchbuffer_reloc64(brw, address.buffer, offset,
+      return intel_batchbuffer_reloc64(&brw->batch, address.buffer, offset,
                                        address.read_domains,
                                        address.write_domain,
                                        address.offset + delta);
    } else {
-      return intel_batchbuffer_reloc(brw, address.buffer, offset,
+      return intel_batchbuffer_reloc(&brw->batch, address.buffer, offset,
                                      address.read_domains,
                                      address.write_domain,
                                      address.offset + delta);
@@ -179,7 +180,9 @@ genX(blorp_exec)(struct blorp_batch *batch,
     * data with different formats, which blorp does for stencil and depth
     * data.
     */
-   brw_emit_mi_flush(brw);
+   if (params->src.enabled)
+      brw_render_cache_set_check_flush(brw, params->src.addr.buffer);
+   brw_render_cache_set_check_flush(brw, params->dst.addr.buffer);
 
    brw_select_pipeline(brw, BRW_RENDER_PIPELINE);
 
@@ -206,6 +209,15 @@ retry:
 
    brw_emit_depth_stall_flushes(brw);
 
+#if GEN_GEN == 8
+   gen8_write_pma_stall_bits(brw, 0);
+#endif
+
+   blorp_emit(batch, GENX(3DSTATE_DRAWING_RECTANGLE), rect) {
+      rect.ClippedDrawingRectangleXMax = MAX2(params->x1, params->x0) - 1;
+      rect.ClippedDrawingRectangleYMax = MAX2(params->y1, params->y0) - 1;
+   }
+
    blorp_exec(batch, params);
 
    /* Make sure we didn't wrap the batch unintentionally, and make sure we
@@ -247,8 +259,6 @@ retry:
    brw->no_depth_or_stencil = false;
    brw->ib.type = -1;
 
-   /* Flush the sampler cache so any texturing from the destination is
-    * coherent.
-    */
-   brw_emit_mi_flush(brw);
+   if (params->dst.enabled)
+      brw_render_cache_set_add_bo(brw, params->dst.addr.buffer);
 }