Merge branch 'master' of libre-riscv.org:shakti-peripherals

[shakti-peripherals.git] / src / peripherals / rgbttl / rgbttl_dummy.bsv

diff --git a/src/peripherals/rgbttl/rgbttl_dummy.bsv b/src/peripherals/rgbttl/rgbttl_dummy.bsv
index a52d5e7db27f36ee367a652d6a0ea0c6dbe3284f..35598d324729affd34701527c59ba2944c748585 100644 (file)
--- a/src/peripherals/rgbttl/rgbttl_dummy.bsv
+++ b/src/peripherals/rgbttl/rgbttl_dummy.bsv
@@ -36,20 +36,20 @@ package rgbttl_dummy;
   import AXI4_Types::*;
 
   interface Ifc_rgbttl_dummy;
-           interface AXI4_Master_IFC#(`ADDR, `DATA, `USERSPACE) master;
-           interface AXI4_Slave_IFC#(`ADDR, `DATA, `USERSPACE) slave;
-      interface Get#(Bit#(1)) de;
-      interface Get#(Bit#(1)) ck;
-      interface Get#(Bit#(1)) vs;
-      interface Get#(Bit#(1)) hs;
-      interface Get#(Bit#(`RGBTTL_WIDTH)) data_out;
+           interface AXI4_Master_IFC#(`PADDR, `DATA, `USERSPACE) master;
+           interface AXI4_Slave_IFC#(`PADDR, `DATA, `USERSPACE) slave;
+      (* always_ready *) interface Get#(Bit#(1)) de;
+      (* always_ready *) interface Get#(Bit#(1)) ck;
+      (* always_ready *) interface Get#(Bit#(1)) vs;
+      (* always_ready *) interface Get#(Bit#(1)) hs;
+      (* always_ready *) interface Get#(Bit#(`RGBTTL_WIDTH)) data_out;
   endinterface
 
   (*synthesize*)
   module mkrgbttl_dummy(Ifc_rgbttl_dummy);
-               AXI4_Slave_Xactor_IFC#(`ADDR,`DATA, `USERSPACE)
+               AXI4_Slave_Xactor_IFC#(`PADDR,`DATA, `USERSPACE)
                             s_xactor<-mkAXI4_Slave_Xactor();
-               AXI4_Master_Xactor_IFC#(`ADDR,`DATA, `USERSPACE)
+               AXI4_Master_Xactor_IFC#(`PADDR,`DATA, `USERSPACE)
                             m_xactor<-mkAXI4_Master_Xactor();
 
       Reg#(Bit#(1)) rg_de <- mkReg(0);