package sdcard_dummy;
`define SDBUSWIDTH 4
`include "instance_defines.bsv"
+ import GetPut::*;
import ClockDiv::*;
import ConcatReg::*;
import Semi_FIFOF::*;
import AXI4_Lite_Types::*;
interface Ifc_sdcard_dummy;
- interface AXI4_Lite_Slave_IFC#(`ADDR, `DATA, `USERSPACE) slave;
+ interface AXI4_Lite_Slave_IFC#(`PADDR, `DATA, `USERSPACE) slave;
interface Get#(Bit#(1)) cmd;
interface Get#(Bit#(1)) clk;
interface Get#(Bit#(`SDBUSWIDTH)) out;
(*synthesize*)
module mksdcard_dummy(Ifc_sdcard_dummy);
- AXI4_Lite_Slave_Xactor_IFC#(`ADDR,`DATA, `USERSPACE)
+ AXI4_Lite_Slave_Xactor_IFC#(`PADDR,`DATA, `USERSPACE)
s_xactor<-mkAXI4_Lite_Slave_Xactor();
Reg#(Bit#(1)) rg_cmd <- mkReg(0);
Reg#(Bit#(1)) rg_clk <- mkReg(0);
Reg#(Bit#(`SDBUSWIDTH)) rg_out <- mkReg(0);
- Reg#(Bit#(`SDBUSWIDTH)) rg_outen <- mkReg(0);
+ Reg#(Bit#(`SDBUSWIDTH)) rg_out_en <- mkReg(0);
Reg#(Bit#(`SDBUSWIDTH)) rg_in <- mkReg(0);
interface cmd = interface Get