[Explaining this](http://bugs.libre-riscv.org/show_bug.cgi?id=178#c146)
to Jean-Paul was amusing and challenging. Much bashing of heads against
-walls and keyboards was involved.
+walls and keyboards was involved. The basic plan: rather than have
+coriolis2 perform an *entire* layout, in a flat and all-or-nothing fashion,
+we need a much more subtle fine-grained approach, where *sub-blocks* are
+laid-out, then *included* at a given level of hierarchy as "pre-done blocks".
+
+Save and repeat.
+
+This apparently had never been done before, and explaining it in words was
+extremely challenging. Through a massive hack (actively editing the underlying
+HDL files temporarily in between tasks) was the only way to illustrate it.
+However once the lightbulb went on, Jean-Paul was able to get coriolis2's
+c++ code into shape extremely rapidly, and this alone has opened up an
+*entire new avenue* of potential for coriolis2 to be used in industry
+for doing much larger ASICs. Which is precisely the kind of thing that
+our NLNet sponsors (and the EU, from the Horizon 2020 Grant) love. hooray.
+Now if only we could actually go to a conference and talk about it.
# POWER ISA decoder and Simulator
# Sponsorship by RaptorCS with a TALOS II Workstation
-TODO http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-March/005291.html
+With many thanks to Timothy from
+[RaptorCS](https://raptorcs.com), we've a new shiny
+online server that needs
+[setting up](http://bugs.libre-riscv.org/show_bug.cgi?id=265).
+This machine is not just a "nice-to-have", it's actually essential for
+us to be able to verify against. As you can see in the bugreport, the idea
+is to bootstrap our way from running IEEE754 FP on a *POWER* system
+(using typically gnu libm), verifying Jacob's algorithmic FP library
+particularly and specifically for its rounding modes and exception modes.
+
+Once that is done, then apart from having a general-purpose library that
+is compliant with POWER IEEE754 which *anyone else can use*, we can use
+that to run unit tests against our[
+hardware IEEE754 FP library](https://git.libre-riscv.org/?p=ieee754fpu.git;a=summary) -
+again, a resource that anyone may use in any arbitrary project - verifying
+that it is also correct. This stepping-stone "bootstrap" method we are
+deploying all over the place, however to do so we need access to resources
+that have correctly-compliant implementations in the first place. Thus,
+the critical importance of access to a TALOS II POWER9 workstation.
# Epic Megagrants
wide interface, we can contract SymbioticEDA to *design* a DDR3 PHY for us,
which both we *and the rest of the worldwide Silicon Community can use
without limitation* because we will ask SymbioticEDA to make the design
-libre-licensed, for anyone to use.
+(and layout) libre-licensed, for anyone to use.
USD 250,000 pays for the mask charges that will allow us to do the 40nm
quad-core ASIC that we have on the roadmap for the second chip. USD
the extremely simple and highly effective hardware but timing-critical
design aspects of the circular loops in the 6600 were recognised by James
Thornton (the co-designer of the 6600) as being paradoxically challenging
-to understand why so few gates could be so effective. Consequently,
-documenting it just to be able to *develop* it is extremely important.
+to understand why so few gates could be so effective (being as they were,
+literally the world's first ever out-of-order superscalar architecture).
+Consequently, documenting it just to be able to *develop* it is extremely
+important.
We're getting to the point where we need to connect the LOAD/STORE Computation
Units up to an actual memory architecture. We've chosen
(Staf is also [sponsored by NLNet](https://nlnet.nl/project/Chips4Makers/)
to create Libre-licensed Cell Libraries, busting through one of the -
-many - layers of NDAs and reducing NREs for ASIC development: I helped him
-put in the submission, and he was really happy to do the Cell Libraries
-that we will be using for LibreSOC's 180nm test tape-out in October 2020.)
+many - layers of NDAs and reducing NREs and unnecessary and artificial
+barriers for ASIC development: I helped him put in the submission, and
+he was really happy to do the Cell Libraries that we will be using for
+LibreSOC's 180nm test tape-out in October 2020.)
# Public-Inbox and Domain Migration
to its ability to not only have a mailing list entirely stored in a
git repository, the "web service" which provides access to that git-backed
archive can be not only mirrored elsewhere, it can be *run locally on
-your own offline machine*. This in combination with the right mailer
-setup can store-and-forward any replies to the (offline-copied) messages,
+your own local machine* even when offline. This in combination
+with the right mailer setup can store-and-forward any replies to the
+(offline-copied) messages, such that they can be sent when internet
+connectivity is restored, yet remain a productive collaborative developer.
Now you know why we absolutely do not accept "slack", or other proprietary
"online oh-so-convenient" service. Not only is it highly inappropriate for
projects / crowdsupply.git / blobdiff