projects / soc.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: c1b0308) | patch
idea: invert pos/neg test in output stage, uses an XOR instead of QTY 2 64-bit
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 14 May 2020 16:20:53 +0000 (17:20 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 14 May 2020 16:20:53 +0000 (17:20 +0100)
commit007b865eb97e970a9b7f7fc6bf06adf5b70ec707
tree6ed2fda0bb4d5c1fba481cb567f96a10825cbdb1tree
parentc1b030839617b1ffd43d305bf702cdb2e10be8f9commit | diff
idea: invert pos/neg test in output stage, uses an XOR instead of QTY 2 64-bit
MUXes and a mess/morass of code
libreriscv diff | blob | history
src/soc/alu/output_stage.py diff | blob | history