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(parent: b0177c8) | patch
add SVSTATE (SVSRR0) to TRAP pipeline
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 4 May 2021 17:40:35 +0000 (18:40 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 4 May 2021 18:33:40 +0000 (19:33 +0100)
commit040920fc27a09cfe864e4ff521ef6f34ebe68faf
tree14fd9b80178ff0aac79990529f973addec696939tree
parentb0177c83b5ff1549deab702c4cd2a506bb762fb6commit | diff
add SVSTATE (SVSRR0) to TRAP pipeline
involves adding svstate to TrapOutputData regspec, and a corresponding
write port to StateRegs, and adding svstate to CompTrapOpSubset
src/soc/fu/trap/main_stage.py diff | blob | history
src/soc/fu/trap/pipe_data.py diff | blob | history
src/soc/fu/trap/trap_input_record.py diff | blob | history
src/soc/regfile/regfiles.py diff | blob | history