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(parent: 239bbde) | patch
Implement a pseudo 1W/2R memory
authorCesar Strauss <cestrauss@gmail.com>
Sun, 17 Apr 2022 18:13:52 +0000 (15:13 -0300)
committerCesar Strauss <cestrauss@gmail.com>
Sun, 17 Apr 2022 18:22:07 +0000 (15:22 -0300)
commit05ed733d78f83ec3c485c1d9f908fdb7f40e098c
tree5a1ad1bc86349b44fe932fef17fc453cf0139498tree
parent239bbdefc79ddf27d282072d3dc73e14823c8611commit | diff
Implement a pseudo 1W/2R memory

This is intended for a XOR-based 6x1RW implementation of a 1R/1W
register file.
It costs 3 x 1RW memory blocks.
src/soc/regfile/sram_wrapper.py diff | blob | history