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(parent: 9b21f0b) | patch
Add sim models for SRAM block.
authorStaf Verhaegen <staf@stafverhaegen.be>
Tue, 6 Apr 2021 18:32:12 +0000 (20:32 +0200)
committerStaf Verhaegen <staf@stafverhaegen.be>
Tue, 6 Apr 2021 18:34:24 +0000 (20:34 +0200)
commit0628a53ddbc0d7913578895f5b3c5715b0016f76
treed85e1a5026e38bf4ccfa139219aea0cef7a3958btree
parent9b21f0b1b28cf3814f553af489b795b068c52b8ccommit | diff
Add sim models for SRAM block.

Both Verilog and VHDL model is provided.
ls180/SPBlock_512W64B8W.v [new file with mode: 0644] blob
ls180/SPBlock_512W64B8W.vhdl [new file with mode: 0644] blob