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(parent: 0dc4f97) | patch
swap over S and W to get SDRAM AD* to line up
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 10 Jun 2021 11:59:37 +0000 (12:59 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 10 Jun 2021 11:59:37 +0000 (12:59 +0100)
commit096caad8418250693c93ccf90047750704adcaa7
treee2706a5e9a64e4cfc520dc6352b658842d232aaftree
parent0dc4f97f52eb24f88b2d94fb3e1f54957c5ce3f8commit | diff
swap over S and W to get SDRAM AD* to line up
src/spec/ls180.py diff | blob | history
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