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(parent: aa33c1b) | patch
add in Vectorised CRs when Rc=1 into ISACaller
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 20 Feb 2021 23:32:50 +0000 (23:32 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 20 Feb 2021 23:32:50 +0000 (23:32 +0000)
commit0fa0da7ccac38dca3c3bfe0d4ab4e15a27367ef2
treefa82f661436ce85ecd88e7f176bf9a193176e739tree
parentaa33c1b9de05e7ff3fbd5ce577f5917f3d142d32commit | diff
add in Vectorised CRs when Rc=1 into ISACaller
src/soc/decoder/isa/caller.py diff | blob | history
src/soc/decoder/isa/test_caller_svp64.py diff | blob | history
src/soc/decoder/power_decoder2.py diff | blob | history