wait for MMU "done" when setting PRTBL and PIDR
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 25 Dec 2021 07:24:11 +0000 (07:24 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 25 Dec 2021 07:24:11 +0000 (07:24 +0000)
commit1018ea09b6d3395c9afe1e3fba869889d5e9140d
treef29b8e37fcba7286cd851bb7eec88cc9dd9d8522
parentfb036eba55efada8a626df383a260b34ef269072
wait for MMU "done" when setting PRTBL and PIDR
src/soc/simple/test/test_core.py