projects / soc.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 5449014) | patch
double the number of lines in the L1 D/I-Cache to match microwatt
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 6 Jan 2022 17:32:46 +0000 (17:32 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 6 Jan 2022 17:32:46 +0000 (17:32 +0000)
commit11489454be1aef4cee4970e50ebf6133492363a6
tree49164a7cf665e209d0e0be5b308e44881fd77112tree
parent5449014d5ea3f27aa7d7296a6eb91e606e288de6commit | diff
double the number of lines in the L1 D/I-Cache to match microwatt
early tests halved the number of lines so as to reduce the size of SRAMs
but the issue is that this is mis-matched against the microwatt.dts
device-tree file
src/soc/experiment/dcache.py diff | blob | history
src/soc/experiment/icache.py diff | blob | history