set power type in fake pll vdd/vss
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 5 Jun 2021 17:38:04 +0000 (17:38 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 5 Jun 2021 17:38:04 +0000 (17:38 +0000)
commit131b93797570728c4158cec388cd3354af104b64
treed5d46d868dce420a4cf8efe3cde2233383e44cc7
parent3d6f1c59e70df22b604249e91cb5ea78f2c067db
set power type in fake pll vdd/vss
experiments10_verilog/pll.py
experiments9/pll.py