Changed ack behaviour for rd (1 clk) and wr (2 clk)
authorAndrey Miroshnikov <andrey@technepisteme.xyz>
Mon, 23 May 2022 18:21:21 +0000 (18:21 +0000)
committerAndrey Miroshnikov <andrey@technepisteme.xyz>
Mon, 23 May 2022 18:21:21 +0000 (18:21 +0000)
commit161451fb9fb76ffc39d4c9b5648da26c87366331
tree5590f0cc485608f10431425cb11178a11467d708
parent3c26e7d042c956c0ff7791b78e19b12a3b6e71ad
Changed ack behaviour for rd (1 clk) and wr (2 clk)
src/spec/simple_gpio.py