projects / soclayout.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: eeb2d5e) | patch
add an SRAM and wishbone to add test (makes it bigger)
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 14 Apr 2021 19:29:22 +0000 (19:29 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 14 Apr 2021 19:29:22 +0000 (19:29 +0000)
commit16e003d52e2590d150541e8b388d92d5c0c6617a
treea3bafb7fdc395b8219f809204bf57c9e2ff79926tree
parenteeb2d5ef99d086f4d1ae757d35613cabae478c2dcommit | diff
add an SRAM and wishbone to add test (makes it bigger)
also enable HFNS.  this to test cocotb-ghdl
experiments10_verilog/add.py diff | blob | history
experiments10_verilog/doDesign.py diff | blob | history