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(parent: 06f09cc) | patch
add two SRAMs, document how to do more
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 19 Apr 2021 17:34:30 +0000 (17:34 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 19 Apr 2021 17:34:30 +0000 (17:34 +0000)
commit177668f4e940511fb73b045fb86963e2ebbbf451
treeee8e07688ec3ec18ac3832135690fa0d187e9158tree
parent06f09ccf63b8a90be45893d2a2dcf5d9d3c241ddcommit | diff
add two SRAMs, document how to do more
experiments10_verilog/add.py diff | blob | history