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(parent: 96b92eb) | patch
investigating why write-enable not getting passed through
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 26 Jun 2020 15:52:34 +0000 (16:52 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 26 Jun 2020 15:52:34 +0000 (16:52 +0100)
commit18aae34636b51c748e96b21e90b206f4a6a657f8
treefa24e4b2d29a71dbb0e5bc4e00a6d7cef5f74c65tree
parent96b92eb50b05be9423cb80ebacae64cc4f3a81c7commit | diff
investigating why write-enable not getting passed through
on nmigen_soc sram
src/soc/bus/test/test_minerva.py diff | blob | history
src/soc/config/test/test_loadstore.py diff | blob | history