Wire up missing CRG / DDR3 clock control / reset signals
authorRaptor Engineering Development Team <support@raptorengineering.com>
Sat, 9 Apr 2022 20:06:12 +0000 (15:06 -0500)
committerRaptor Engineering Development Team <support@raptorengineering.com>
Sat, 9 Apr 2022 20:06:12 +0000 (15:06 -0500)
commit19ed0026e91b2dd351fbd2d692fb2c6f45b42622
tree97a476b9ea322fff2256b81b4c0ee8351b6d4e03
parentcb6c333200bd5d1dbeeb2971a8f378ee5123deea
Wire up missing CRG / DDR3 clock control / reset signals
src/ecp5_crg.py
src/ls2.py