add SDRAM Configuration Record
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 18 Feb 2022 19:41:23 +0000 (19:41 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 18 Feb 2022 19:41:23 +0000 (19:41 +0000)
commit1fa0fb1b53ca9c3928ff5b275b5c260ce301afbb
tree56fbc85db00766f8d1c09718462f89486c7bd1ea
parent88a7bb476664778400e29a5c1b929fa9a2d74cd6
add SDRAM Configuration Record
src/soc/bus/sdr_ctrl.py