Reroute clk so PLL output clock is used as sys_clk.
authorStaf Verhaegen <staf@fibraservi.eu>
Thu, 3 Jun 2021 19:59:56 +0000 (21:59 +0200)
committerStaf Verhaegen <staf@fibraservi.eu>
Thu, 3 Jun 2021 19:59:56 +0000 (21:59 +0200)
commit227a0f69bd5065d2bf098a70f05cf68eabebaf86
treee886ac7d3e54832ccdd77059c468c1884ee78646
parent19547d0c7b9ad74e4af844b13fa63d0401ad7250
Reroute clk so PLL output clock is used as sys_clk.
experiments9/non_generated/full_core_4_4ksram_libresoc_recon.v
experiments9/non_generated/full_core_4_4ksram_litex_ls180_recon.v