MMU lookup DSISR load bit inverted in LoadStore1
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 4 Dec 2021 11:46:34 +0000 (11:46 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 4 Dec 2021 11:46:34 +0000 (11:46 +0000)
commit2996b0b14d6c90bc1b79a08651244f342dd428c2
treefee3b7f3afeaf0bac2124a37cca99f2d3147230b
parente050db8c0c19db096689591c26118d2a89f0585b
MMU lookup DSISR load bit inverted in LoadStore1
src/soc/fu/ldst/loadstore.py
src/soc/simple/test/test_issuer_mmu.py