add enable/disable arguments (not ideal but it works) to issuer_verilog.py
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 13 Nov 2020 15:48:21 +0000 (15:48 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 13 Nov 2020 15:48:21 +0000 (15:48 +0000)
commit2a542d127ee4fdb0d3a1f34816288fcdba4c759e
treea82a0f3b5a361682ac65c2e591a85fdba7814ee1
parent63e497cbe41f512f28f7f11aa29f83cf4bb27015
add enable/disable arguments (not ideal but it works) to issuer_verilog.py
src/soc/simple/issuer_verilog.py