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(parent: 40fd5c0) | patch
same as shiftrot, split out separate pipelines for logical
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 20 Feb 2022 23:51:32 +0000 (23:51 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 20 Feb 2022 23:51:32 +0000 (23:51 +0000)
commit2b6da534d53396208ddb6b40fb8c13f4ad7d4058
tree4452750bee62b10271f6feb655fe2dca87a210dctree
parent40fd5c0dd27fd8b586a14531eaa1bd7414132cf1commit | diff
same as shiftrot, split out separate pipelines for logical
stages in order to meet FPGA timing
src/soc/fu/logical/pipeline.py diff | blob | history