add verilog build option, make DDR3 PHY optional, add UART pins
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 14 Feb 2022 10:34:48 +0000 (10:34 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 14 Feb 2022 10:34:48 +0000 (10:34 +0000)
commit2c35e5716c5239d0bce4bee08733029e451c1d08
treebdf34c619c78250e16bccaff32a6f940665fa78d
parenta0e02bc6026bbc0105f61cbc8262dec124cee49a
add verilog build option, make DDR3 PHY optional, add UART pins
src/ls2.py