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(parent: 91a0c43) | patch
Separate nest and core clocks
authorRaptor Engineering Development Team <support@raptorengineering.com>
Mon, 11 Apr 2022 19:33:25 +0000 (14:33 -0500)
committerRaptor Engineering Development Team <support@raptorengineering.com>
Mon, 11 Apr 2022 19:33:25 +0000 (14:33 -0500)
commit2d7021ba09c3e08e1780bf73c26deeaccf689221
tree9038901e4a927c5ccc4ae053f6c9007e71b3e35ctree
parent91a0c4363cbd62ff506bcaad2ee7f57d42b28c7dcommit | diff
Separate nest and core clocks

Add async bridges between CPU and Wishbone
downconverters

Switch Raptor Versa 85 board to 100MHz
nest and 50MHz core

Verified to function on Raptor Versa 85
board
simsoc.ys diff | blob | history
src/ecp5_crg.py diff | blob | history
src/ls2.py diff | blob | history