add opencores SDRAM verilog wrapper
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 17 Feb 2022 17:09:21 +0000 (17:09 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 17 Feb 2022 17:09:21 +0000 (17:09 +0000)
commit2e3b1eaed4122461c936f923c8c91b73d7848819
tree39b58b85601c36a5944eca5922bce7ac9811ce22
parentc9129d8a0f92b04702c3153b644039e764857419
add opencores SDRAM verilog wrapper
src/soc/bus/sdr_ctrl.py [new file with mode: 0644]
src/soc/experiment/icache.py