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(parent: 00629c4) | patch
interconnect/stream: set default AsyncFIFO depth to None and add depth parameter...
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Wed, 5 Aug 2020 10:11:12 +0000 (12:11 +0200)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Wed, 5 Aug 2020 10:11:12 +0000 (12:11 +0200)
commit303d6cca7e4139fcc9bc7ea80634b9c78048928a
tree1bc04558035c3a4d03c769ca9d826f01c3ad7857tree
parent00629c45b0ecb44149893439d040d4b4267ba4eacommit | diff
interconnect/stream: set default AsyncFIFO depth to None and add depth parameter to ClockDomainCrossing.
litex/soc/interconnect/stream.py diff | blob | history