add edge-triggering to dcache/mmu "valid"
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 15 Sep 2020 19:36:18 +0000 (20:36 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 15 Sep 2020 19:36:18 +0000 (20:36 +0100)
commit3097f9d418265e46eb027849aad8f8194a074390
treea4f4f32cd20f0890983a7f3b249a0eb1eaa8db64
parentc1fcd5c907e243795cb9f44f475c59fa603ba2d5
add edge-triggering to dcache/mmu "valid"
src/soc/fu/mmu/fsm.py