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(parent: acd1da7) | patch
add misaligned load through MMU (which is incorrectly succeeding without error)
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 14 May 2021 10:30:53 +0000 (11:30 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 14 May 2021 10:30:53 +0000 (11:30 +0100)
commit31a3aaccdc3cc7d03ed840e944be67ff6e0512cc
treec0073aecb62da0f00a4625be05cb078d8093326atree
parentacd1da7b3604e36deba6be59226eeeaacd0ccf60commit | diff
add misaligned load through MMU (which is incorrectly succeeding without error)
src/soc/experiment/test/test_ldst_pi.py diff | blob | history