rename pll out signal to out_v in "fake" pll cell
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 25 May 2021 11:37:47 +0000 (11:37 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 25 May 2021 11:37:47 +0000 (11:37 +0000)
commit34eaf7feae8e6835b69fbb7b1582dd0b9905f2ef
treeef15b7091e4c6a873e13894702bf78e122878929
parent9b2ce502a7b2acf0a6fd9dc65868240d08d96efc
rename pll out signal to out_v in "fake" pll cell
experiments9/pll.py