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(parent: fdf3b06) | patch
use nmigen Memory in I-Cache for TLB Lookups
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 30 Jan 2022 18:16:37 +0000 (18:16 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 30 Jan 2022 18:16:37 +0000 (18:16 +0000)
commit3cd21fbd76fef3403a42f0baf2d234be4bea7957
tree5b77fa6910ea251ebc3a8929d99c58e08b6b7217tree
parentfdf3b0665dc8ae03c35c636d16473f6fc9060300commit | diff
use nmigen Memory in I-Cache for TLB Lookups
surprisingly this makes the Libre-SOC core *50% faster* than microwatt
when running under verilator, despite only being a FSM
src/soc/experiment/icache.py diff | blob | history