missing ports from issuer, when doing verilog
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 22 Jul 2020 20:27:42 +0000 (21:27 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 22 Jul 2020 20:27:42 +0000 (21:27 +0100)
commit3cd49ba3ba82391f6586495fc0e429828bb7c149
treeb68fa7520d5d8cefae75ea581f0039e03319f2f6
parent53c378fd3f2359e9866b95eb42b2eac8034d8a74
missing ports from issuer, when doing verilog
src/soc/simple/issuer.py