whoops, fake pll/mem need vss/vdd
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 5 Jun 2021 17:34:32 +0000 (17:34 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 5 Jun 2021 17:34:32 +0000 (17:34 +0000)
commit3d6f1c59e70df22b604249e91cb5ea78f2c067db
tree943af342e8ad778e3e5ab49d7fe159a90d857ec6
parent0014e1c4e64c42486f50b1b7abf78563cbf60b1e
whoops, fake pll/mem need vss/vdd
experiments10_verilog/pll.py
experiments9/LibreSOCMem.py
experiments9/pll.py