add misaligned ld/st to trigger an exception
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 3 Dec 2021 15:22:10 +0000 (15:22 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 3 Dec 2021 15:22:10 +0000 (15:22 +0000)
commit3e6d3a54cc50c4b4b0b8757986b3baad458ebe6b
treed8f9875c0a04099f83e9679b65c4176798ec4e0b
parentda20ed1272a96c39a28d3040480c2191e76fa7f3
add misaligned ld/st to trigger an exception
src/soc/simple/test/test_issuer_mmu.py