add msr_pr bit in PortInterface
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 11 May 2021 10:46:33 +0000 (11:46 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 11 May 2021 10:46:33 +0000 (11:46 +0100)
commit41a5bff9dbab0d8de3617ae1dd0b481447ffae5e
tree04458cb4773db6e638ea1798570109d233c86fa2
parentc1dfbf3452e7411402b20901f3d1ccef5fbb0326
add msr_pr bit in PortInterface
src/soc/experiment/pimem.py