add debugging and buffering to CacheRam
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 22 Apr 2021 22:59:56 +0000 (23:59 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 22 Apr 2021 22:59:56 +0000 (23:59 +0100)
commit41e1c2e22d32f14249444e7dd2b79c247755aa97
tree1d8ebc883ab10be8ea2fdc783d8685c53c1685d5
parent41912685724c24a9689f3cf521cb9e8066525d68
add debugging and buffering to CacheRam
src/soc/experiment/cache_ram.py
src/soc/experiment/dcache.py