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(parent: 5c65928) | patch
hook up dcache wb_in/out to PortInterfaceBase Wishbone Record
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 30 Apr 2021 12:48:34 +0000 (13:48 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 30 Apr 2021 12:48:34 +0000 (13:48 +0100)
commit45bf7f5d94e9b6315dcc7c8170c5762e82389c9d
tree83e24f24fb7be1e3eaafbd56abb144cb8248aacdtree
parent5c659283f4bffd0344dd8bfae663ed369d33023fcommit | diff
hook up dcache wb_in/out to PortInterfaceBase Wishbone Record
src/soc/fu/mmu/fsm.py diff | blob | history