try different MEMTEST_xxx sizes with 64 bit bus width
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 23 Jul 2020 19:28:37 +0000 (20:28 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 23 Jul 2020 21:43:07 +0000 (22:43 +0100)
commit48241fac1239dba697be28f72e68a741a0e75eb5
tree506fbae460a4f23833caf9bdaed6ecef63e3364e
parent71a2b2d0c3d12f1091f0648cd45684e2eaaade9b
try different MEMTEST_xxx sizes with 64 bit bus width
src/soc/litex/sim.py