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Import the JTAG interface code as used for the Chips4Maker pilot Retro-uC
authorStaf Verhaegen <staf@stafverhaegen.be>
Sun, 27 Aug 2017 20:05:24 +0000 (22:05 +0200)
committerStaf Verhaegen <staf@stafverhaegen.be>
Sun, 27 Aug 2017 20:05:24 +0000 (22:05 +0200)
commit493ecad3a8956d5296d6593b5970867cd67f9bae
tree970ad059b9fbacab845ec960b6bb55bfe7c21ac4tree
Import the JTAG interface code as used for the Chips4Maker pilot Retro-uC

This code has currently been tested in FPGA through a buspirate so should
already be functional.
20 files changed:
.gitignore [new file with mode: 0644] blob
bench/vhdl/idcode.vhdl [new file with mode: 0644] blob
bench/vhdl/sampleshift.vhdl [new file with mode: 0644] blob
rtl/vhdl/c4m_jtag_idblock.vhdl [new file with mode: 0644] blob
rtl/vhdl/c4m_jtag_ioblock.vhdl [new file with mode: 0644] blob
rtl/vhdl/c4m_jtag_iocell.vhdl [new file with mode: 0644] blob
rtl/vhdl/c4m_jtag_irblock.vhdl [new file with mode: 0644] blob
rtl/vhdl/c4m_jtag_pkg.vhdl [new file with mode: 0644] blob
rtl/vhdl/c4m_jtag_tap_controller.vhdl [new file with mode: 0644] blob
rtl/vhdl/c4m_jtag_tap_fsm.vhdl [new file with mode: 0644] blob
sim/cocotb/c4m_jtag.py [new file with mode: 0644] blob
sim/cocotb/controller/Makefile [new file with mode: 0644] blob
sim/cocotb/controller/c4m_jtag.py [new symlink] blob
sim/cocotb/controller/test.py [new file with mode: 0644] blob
sim/cocotb/dual_parallel/Makefile [new file with mode: 0644] blob
sim/cocotb/dual_parallel/c4m_jtag.py [new symlink] blob
sim/cocotb/dual_parallel/dual_parallel.vhdl [new file with mode: 0644] blob
sim/cocotb/dual_parallel/test.py [new file with mode: 0644] blob
sim/cocotb/dual_serial/TODO [new file with mode: 0644] blob
sim/ghdl/bench_idcode.sh [new file with mode: 0755] blob