invert Cat order, use 3 zeros (3 bits)
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 14 Feb 2019 04:32:09 +0000 (04:32 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 14 Feb 2019 04:32:09 +0000 (04:32 +0000)
commit4ccb4d59bd50c5d5bff9008dac0ca034fc2d8e9a
treeb3ace5ea4c53446e1b10f54b58d612f6eefa3982
parent7fe4616cc217cc2b8bf5243f931498d51965ad44
invert Cat order, use 3 zeros (3 bits)
src/add/nmigen_add_experiment.py