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radeonsi/gfx10: set PA_CL_VS_OUT_CNTL with CONTEXT_REG_RMW to fix edge flags
authorMarek Olšák <marek.olsak@amd.com>
Wed, 21 Aug 2019 04:18:17 +0000 (00:18 -0400)
committerMarek Olšák <marek.olsak@amd.com>
Tue, 27 Aug 2019 20:16:08 +0000 (16:16 -0400)
commit4dde40908fdb20ca3efce4a138293ddf829e2c0b
tree54d58eb5374a9b8d7444d554fd97b81c6d9be08etree
parent1426acf9e7ecba1a252b68979f8721b26fc73f44commit | diff
radeonsi/gfx10: set PA_CL_VS_OUT_CNTL with CONTEXT_REG_RMW to fix edge flags

We need two different values of the register, one for NGG and one for
legacy, in order to fix edge flags for the legacy pipeline.

Passing the ngg flag to emit_clip_regs would be too complicated,
so CONTEXT_REG_RMW is used for partial register updates.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
src/gallium/drivers/radeonsi/si_gfx_cs.c diff | blob | history
src/gallium/drivers/radeonsi/si_shader.h diff | blob | history
src/gallium/drivers/radeonsi/si_state.c diff | blob | history
src/gallium/drivers/radeonsi/si_state.h diff | blob | history
src/gallium/drivers/radeonsi/si_state_shaders.c diff | blob | history