rename intermediate signals to wr_wait/rd_wait
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 13 May 2019 19:03:23 +0000 (20:03 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 13 May 2019 19:03:23 +0000 (20:03 +0100)
commit4e1c12403ea6e9ff79ca9a6d6299ec8a8eb66bd8
tree4863414adb9cc92c594f9cfa9baf3cdece4e80f9
parent511543b793aeaa2d75016d9cd9aac4c50f3fc9f7
rename intermediate signals to wr_wait/rd_wait
src/scoreboard/fu_dep_cell.py
src/scoreboard/fu_fu_matrix.py