add vss/vdd as pins, gets the net into the VST
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 5 Jun 2021 17:45:00 +0000 (17:45 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 5 Jun 2021 17:45:00 +0000 (17:45 +0000)
commit4f3fce32074946c452fe9089cec271a6d5843e59
tree2517eeea04f22a9de00e5e5ce32960d13de14d7b
parent131b93797570728c4158cec388cd3354af104b64
add vss/vdd as pins, gets the net into the VST
experiments10_verilog/pll.py
experiments9/pll.py